CAT34TS02
http://onsemi.com
7
Pin Description
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master (Host).
SDA: The Serial Data I/O pin receives input data and
transmits data stored in the internal registers. In transmit
mode, this pin is open drain. Data is acquired on the positive
edge, and is delivered on the negative edge of SCL.
A0, A1 and A2: The Address pins accept the device address.
These pins have onchip pulldown resistors.
EVENT
: The opendrain EVENT
pin can be programmed
to signal over/under temperature limit conditions.
PowerOn Reset (POR)
The CAT34TS02 incorporates PowerOn Reset (POR)
circuitry which protects the device against powering up to
invalid state. The TS component will power up into
conversion mode after V
CC
exceeds the TS POR trigger
level and the SPD component will power up into standby
mode after V
CC
exceeds the SPD POR trigger level. Both the
TS and SPD components will power down into Reset mode
when V
CC
drops below their respective POR trigger levels.
This bidirectional POR behavior protects the CAT34TS02
against brownout failure following a temporary loss of
power. The POR trigger levels are set below the minimum
operating V
CC
level.
Device Interface
The CAT34TS02 supports the InterIntegrated Circuit
(I
2
C) and the System Management Bus (SMBus) data
transmission protocols. These protocols describe serial
communication between transmitters and receivers sharing
a 2wire data bus. Data ow is controlled by a Master
device, which generates the serial clock and the START and
STOP conditions. The CAT34TS02 acts as a Slave device.
Master and Slave alternate as transmitter and receiver. Up to
8 CAT34TS02 devices may be present on the bus
simultaneously, and can be individually addressed by
matching the logic state of the address inputs A0, A1, and
A2.
I
2
C/SMBus Protocol
The I
2
C/SMBus uses two wires, one for clock (SCL) and
one for data (SDA). The two wires are connected to the V
CC
supply via pullup resistors. Master and Slave devices
connect to the bus via their respective SCL and SDA pins.
The transmitting device pulls down the SDA line to
transmit a 0 and releases it to transmit a 1.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 20).
START
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a wakeup call to all Slaves. Absent a
START, a Slave will not respond to commands.
STOP
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP tells the Slave that no more data will be written
to or read from the Slave.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8bit
serial Slave address. The first 4 bits of the Slave address (the
preamble) select either the Temperature Sensor (TS)
registers (0011) or the EEPROM memory contents (1010),
as shown in Figure 21. The next 3 bits, A2, A1 and A0, select
one of 8 possible Slave devices. The last bit, R/W
, specifies
whether a Read (1) or Write (0) operation is being
performed.
Acknowledge
A matching Slave address is acknowledged (ACK) by the
Slave by pulling down the SDA line during the 9
th
clock
cycle (Figure 22). After that, the Slave will acknowledge all
data bytes sent to the bus by the Master. When the Slave is
the transmitter, the Master will in turn acknowledge data
bytes in the 9
th
clock cycle. The Slave will stop transmitting
after the Master does not respond with acknowledge
(NoACK) and then issues a STOP. Bus timing is illustrated
in Figure 23.
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